| 摘要 |
PCT No. PCT/JP96/01447 Sec. 371 Date Mar. 17, 1998 Sec. 102(e) Date Mar. 17, 1998 PCT Filed May 29, 1996 PCT Pub. No. WO97/00518 PCT Pub. Date Jan. 3, 1997A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation. The inhibiting function makes it possible to provide a memory device having compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
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