发明名称 EMITTER COUPLED LOGIC AMPLIFIER CIRCUIT USING ACTIVE LOAD
摘要 PURPOSE: An emitter coupled logic amplifier circuit using an active load is provided to improve a switching speed by shortening a state transition time of an output signal by compensating a charge/discharge time of a loading capacitor. CONSTITUTION: The emitter coupled logic amplifier circuit using an active load comprises: a current switch(20) of differential amplifier type including a first and a second transistor whose emitters are connected each other, to receive an input signal to a base of the first transistor and to receive a reference voltage to a base of the second transistor, and to output a comparison signal by comparing the input signal and the reference voltage through a collector of the first transistor; an emitter follower(24) including an amplifying transistor having a collector connected to a first supply voltage and to receive and amplify an output signal of the current switch through a base, and an active load transistor(Q15) having an emitter connected to an emitter of the amplifying transistor; and a biasing unit(22) to bias the base of the active load transistor of the emitter follower, wherein the biasing unit biases the active load transistor with a constant voltage at a normal state, and biases the active load transistor with a voltage level higher than the constant voltage when the input signal goes from a first level to a second level, and biases the active load transistor with a voltage level lower than the constant voltage when the input signal goes from a second level to a first level.
申请公布号 KR20000000937(A) 申请公布日期 2000.01.15
申请号 KR19980020890 申请日期 1998.06.05
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JEONG, JAE CHEON
分类号 H03K19/086;(IPC1-7):H03K19/086 主分类号 H03K19/086
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