SEMICONDUCTOR MEMORY DEVICE AND REDUCTION METHOD OF TEST TIME

摘要

PURPOSE: A semiconductor memory having a reduction device of test time and a reduction method of test time are provided. CONSTITUTION: The long cycle disturbance test device for the semiconductor memory comprises: an inputting device(1) to logically operate by inputting a battery back-up mode signal and a parallel test signal; a decoding device(2) to decode the logically operated output signal and the parallel test signal; a outputting device(3) to output a transmitted signal by decoding from the decoding device.