SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE USING VARIABLE EXTERNAL POWER VOLTAGE

摘要

PURPOSE: An SDRAM is provided to improve tSAC(required time from an activity of clock signals to an output of effective data) by using variable internal power voltage. CONSTITUTION: The SDRAM comprises a data output control circuit(15) applied a first internal power voltage(IVC1) through a first internal voltage generating circuit(11); and a peripheral circuit(17) applied a second internal power voltage(IVC2) through a second internal voltage generating circuit(13), wherein the voltage levels of the first internal power voltage(IVC1) and the second internal power voltage(IVC2) are different from each other. The data output control circuit(15) includes an output buffer(19) for receiving a data of data output lines and outputting a data to a output pad(23) and an output control clock signal generating part(21) for receiving an external clock signal and generating an output control clock signal.