BIT-REVERSED ADDRESS GENERATOR OF A FAST FOURIER TRANSFORM DEVICE

摘要

PURPOSE: A bit-reversed address generator is provided to improve an operation speed of a reverse carry propagate adder by inputting to the adder only one of data from an auxiliar register and data from an index register whose added result is changed. CONSTITUTION: The bit-reversed address generator of a fast fourier transform device comprises: an auxiliar register(41) for storing an initial address of a data block required to perform a fast fourier transform; an index register(43) for storing an index value having point information of the fast fourier transform; a point detector(45) for detecting the point information of the index value stored in the auxiliar register to generate a bypass control signal; a first bypass part(42) for receiving the bypass control signal and the address in the auxiliar register to limitedly output one of the address having a magnitude determined by the bypass control signal; a second bypass part(44) for receiving the bypass control signal and the index values in the auxiliar register, to limitedly output one of the index values having a magnitude determined by the bypass control signal; and a reverse carry propagate adder(46) for adding the address from the first bypass part and the index value from the second bypass part to feed an added result back to the auxiliar register.