| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof which has dummy regions for the step reduction suppressing the parasitic capacitance from growing, without increasing the manufacturing process. SOLUTION: On regions isolated by trenches 3 of a main surface of a semiconductor substrate 1, dummy regions 43a, 43b leaving the main surface thereon for reducing steps in following process are provided and include n- and p-type impurity regions 20a, 20b at specified depths from the surfaces of the dummy regions 43a, 43b, respectively, p-n junctions result at the bottoms of the impurity regions 20a, 20b and hence depletion layers expand to the p-n junctions to reduce the parasitic capacitance between conductive wirings 13 crossing above the dummy regions 43a, 43b. The impurity regions 20a, 20b are formed at once by the impurity implanting to form source/drain regions 9a, 10a, 9b, 10b of p- and n-channel transistors at active regions.
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