CLOCK MONITOR CIRCUIT AND SYNCHRONIZATION SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a clock monitor circuit that can monitor whether or not a clock signal is received independently of the period of the clock signal. SOLUTION: This clock monitor circuit is provided with a 1st (2nd) delay and clock signal generating circuit 10(20) that receives respectively a clock signal (inverse of clock signal) fixed to a low level when stopped, delays the clock signal for a prescribed time and generates a 1st (2nd) signal which never reaches a low level, and with an OR circuit 30 that operates the logical sum of the 1st and 2nd signals to generate a step clock signal SCK.