| 摘要 |
PROBLEM TO BE SOLVED: To realize an efficient layout of circuit elements constituting an integrated circuit, without being influenced by the multiformity of the shape, size, etc., of the circuit elements. SOLUTION: Arbitrary signals concerning a plurality of logic blocks 2 constituting an LSI chip 1 are selected to determine a clockwise or counterclockwise flow 4 of signals, a plurality of logic blocks 2 are disposed along the flow 4 route of the signals, and a plurality of logic blocks 2 are replaced across the signal flow 4 so as to minimize the total of the wiring lengths between the plurality of logic blocks 2, dead space value, etc., to optimize the layout and output as a floor plan.
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