发明名称 CLOCK CHANGEOVER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To attain network synchronization by preventing a free-run state of a station when clock supply is interrupted from a digital clock supply device DCS. SOLUTION: A 1st input port 10 receives a DCS clock (a), a 2nd input port 12 receives a transmission line extracted clock (b), and a 3rd port 14 outputs a clock signal required for a station. The DCS clock (a) is given to a selector 22 as a clock (f) via a frequency divider 20. A selector 24 selects the DCS clock (a) or the transmission line extracted clock (b) and the selected clock is given to a phase locked oscillator PLO 26 as a clock (c). The PLO 26 receives a clock signal generated by a prescribed DCS and oscillates a clock signal based on the clock signal just before interruption of the clock signal when the input of the clock signal is interrupted. The PLO 26 generates a prescribed clock (d) based on the received clock (c) and gives the clock (d) to the selector 22 as a clock (e) via a frequency divider 28. The selector 22 selects the clock (e) or (f) and gives the selected clock to a device in the station.
申请公布号 JP2000013366(A) 申请公布日期 2000.01.14
申请号 JP19980173081 申请日期 1998.06.19
申请人 OKI ELECTRIC IND CO LTD 发明人 SUZUKI YOSHIYA
分类号 H03L7/00;H04L7/00;H04L12/00 主分类号 H03L7/00
代理机构 代理人
主权项
地址