发明名称 |
METHOD AND DEVICE FOR PREPARING TEST PATTERN OF LOGIC CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a device for preparing the test pattern of a logic circuit capable of obtaining a high rate of failure detection with a compact test pattern. SOLUTION: The device for preparing the test pattern of a logic circuit is provided with a means 112 to set the difference between the number of times that a gate input signal line should be selected (the product of the probability of selecting the gate input signal line and the number of times that the gate becomes an object of justification operation and that an input signal line for which a signal value 0 or 1 is allotted is selected) and the number of times that the gate input signal line is actually selected as bias, a means 116 to obtain the probability of selecting the gate input signal line, and a mans 140 to select the gate input signal line to set 0 and 1 according to the selection provability in justification processing used for preparing the test pattern of a logic circuit. Random selection according to the selection probability (2) and selection by a random target value on a controllability scale may be adopted (3) as well as selection by the probability of selecting the gate input signal line (1) as selection criteria.
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申请公布号 |
JP2000009813(A) |
申请公布日期 |
2000.01.14 |
申请号 |
JP19980172693 |
申请日期 |
1998.06.19 |
申请人 |
HITACHI LTD |
发明人 |
NATSUME KOICHIRO;HATAKEYAMA KAZUMI;HIKONE KAZUFUMI |
分类号 |
G01R31/317;G01R31/3183;G06F17/50;(IPC1-7):G01R31/317;G01R31/318 |
主分类号 |
G01R31/317 |
代理机构 |
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主权项 |
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地址 |
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