| 摘要 |
PROBLEM TO BE SOLVED: To end a burst mode halfway, without increasing the number of system commands, by operating in the burst mode and usual mode and ending the burst mode, utilizing one command used in the usual operation mode. SOLUTION: When a mode register set command is inputted synchronously with an internal clock signal CLK with a burst signal at H-level, an NAND gate NAND1 and inverter INV1 in a second circuit 12 enable a mode register setting signal during other mode operation than the burst mode whereby the mode register set command is usable as an original mode register setting command. When the mode register set command is generated during the burst mode operation, the burst stop signal is enabled synchronously with the internal clock signal CLK in a first circuit 11, thereby ending the burst mode operation.
|
