发明名称 PARALLEL LOGICAL SIMULATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To enhance a parallel effect and to efficiently execute a logical simulation by making a combination circuit part simulation processor obtain input information from a control processor as necessary and operate asynchronously with a simulation clock. SOLUTION: A control processor 100 controls a time, clock information, input information and output information in a simulation system of a clock synchronization-type zero delay circuit. A combination circuit part simulation processor 101 obtains input information from the control processor 100, executes the simulation of the combination circuit part and delivers output information to the control processor 100. A synchronization circuit part simulation processor 120 obtains clock information from the control processor 100 and input information of the synchronization circuit part from the combination circuit part simulation processor 101, executes the simulation of the synchronization circuit part and delivers the result to the control processor 100.
申请公布号 JP2000011016(A) 申请公布日期 2000.01.14
申请号 JP19980169494 申请日期 1998.06.17
申请人 HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD 发明人 FUKASE YOSHIHIRO;TOMITA HIROSHI
分类号 G06F17/50;G06F11/25;G06F15/16;(IPC1-7):G06F17/50 主分类号 G06F17/50
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