DEVICE AND METHOD FOR VERIFYING LOGICAL CIRCUIT IN SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shorten time required for the verification of a logical circuit by extracting a cell necessary for verification from plural cells included in a core and using the extracted cell as a cell to be processed in respect to a logical circuit verification device suitable for the verification of a logical circuit in a semiconductor integrated circuit including a core having ended the execution of logical timing verification in a part of the circuit. SOLUTION: The logical circuit verification device for verifying a semiconductor integrated circuit including a core and a new circuit is provided with a timing verification cell extraction part 12 for extracting a timing verification cell requiring timing verification when the core and the new circuit are combined from cells included in the core and a delay calculation cell extraction part 14 for extracting a delay calculation cell requiring the calculation of delay time when the core and the new circuit are combined from the cells included in the core. At the time of executing simulation, prescribed processing is executed only for the extracted cells.