| 摘要 |
PROBLEM TO BE SOLVED: To avoid a runaway occurring when a process is performed again in array chain transfer mode and restarted after being interrupted by providing a latch circuit which stores the head address of a transfer parameter memory and a latch circuit which stores the number of all transfer blocks transferred to a TCR latch. SOLUTION: The latch circuit SAR latch 2 of a transfer source address register and a register FBSAR 11 which stores the head address of the transfer parameter memory dedicated to the array chain transfer mode are provided in the same addresses where a transfer source address register is set. In the same addresses where a transfer counter register is set, a TCR latch 6 and a register FBTCR 12 which stores the total number of transfer block are provided. Consequently, when a DMA request for the same DMA transfer is accepted, the head address of the transfer parameter memory is specified from the FBSAR 11 and the contents of the FBTCR 12 are transferred to the TCR latch 6, so an array state operates normally and no runaway is caused.
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