Clock generator with multiple feedback paths including a delay locked loop path

摘要

The present invention encompasses the use of multiple feedback paths in a clock source for an integrated circuit device to maintain phase lock to an external clock. It is further contemplated by the present invention that feedback paths are provided from the internal clock distribution path and from a matching path that approximates the delay of the clock distribution path. The matching path may comprise a delay locked loop. Feedback from the clock distribution path is used in normal operation and feedback from the matching path is used when the internal clock distribution path is disabled. The clock source of the present invention also may implement power management functions.