| 摘要 |
1316807 Data processing WESTERN ELECTRIC CO Inc 4 June 1970 [4 June 1969] 26959/70 Heading G4A [Also in Division H4] A data processing system includes buffer means adapted to be connected to a plurality of data lines to record line status data defining the functional condition of said lines and input and output data associated with each of said lines, first control means adapted to generate and transmit address signals to said buffer means to obtain said line status and said input data from said buffer means, and second control means adapted to respond to signals generated by said first control means and operative concurrently therewith to process said input data and to transmit said output data to said buffer means in accordance with said line status data. As described a buffer processor 110 serves lines 120, there being three types of buffers on respectives ones of which data lines having one of three data transmission rates and/or formats are terminated. Each buffer is an autonomously operating character assembling/disassembling unit acting as an interface between the parallel format used in the processor and the serial format used over the data lines. Each buffer responds to its address on bus 121 and accepts output data from the bus or transmits line status and input data to the bus. The addresses are generated by circuit 116 which operates in one of three modes, viz high, intermediate, and normal priority. Only specified types of buffers (A, B, and C), selected on the basis of data rates, are serviced in each mode, the particular buffers to be serviced being selected by control words stored in buffer store 130. Work in the normal mode is only performed if no intermediate or high priority tasks are outstanding. Normal or intermediate mode operations are interrupted every 1�25 msecs. to cause a transfer into the high priority mode. Input data received from addressed buffers via circuit 116 are processed by circuit 117 which assembles the characters for storage in buffer 130. Output data is received from buffer 130 by circuit 117 and transmitted to the appropriate line buffers, addressed by circuit 116, via line 121. When circuit 116 obtains input data from an addressed buffer it stores the address of that buffer, sets an input/output flag, sets a "request" flip-flop, and adjusts a "buffer type" flip-flop; similar actions also occur when status data indicating that a line is requesting service is received. Circuit 117 responds to the "request" flip-flop, circuit 116 being prevented from operating further until that flip-flop is reset, by taking over the data recorded in circuit 116, and by resetting the "request" flip-flop. Circuit 116 is then free to continue servicing further data line buffers. In the event that circuit 116 again sets the "request" flip-flop, indicating a further service request, before circuit 117 has finished processing. The previous data, then no further action occurs until circuit 117 completes its current tasks. The main data processing system which the buffer processor serves includes a central processor 100 and a main memory system 140 which may include magnetic disc and tape files and associated controllers. A control circuit 113 includes four independent sequencing circuits for controlling the transfer between the buffer store 130 and the appropriate file in the main store 140. An instruction queue in store 130 is uniquely associated with each sequencing circuit and specifies the task to be performed, the corresponding addresses of data in store 130, and an identification of the file in the main memory involved in the transfer. The control unit 113 also includes a priority network for allocating, to each sequencing unit, access to the bus 141 in accordance with a defined priority plan. |
