| 摘要 |
A method for fabricating a memory device, using a butt contact opening, and an overlying SAC structure, to allow connection between a gate structure, and an active device region, in a semiconductor substrate, has been developed. This invention features the use of an organic layer, protecting regions of the memory device from an dry etch procedure, that is used to remove insulator from the top surface, of a portion of the gate structure. A SAC structure, in a SAC opening, supplies the desired connection, via contact to both an active device region, and to the portion of gate structure, that is without the capping insulator.
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