发明名称 Structure and method for measuring interface resistance in multiple interface contacts and via structures in semiconductor devices
摘要 A structure and method is shown for measuring a plug and interface resistance values of an inter-layer contact structure in a semiconductor device. An inter-layer contact plug interconnects two metal layers in the semiconductor device forming a pair of plug to metal layer interfaces. A conductive trace is formed in an inter-metal dielectric layer between the metal layers, where the conductive trace couples the conductive plug to a pair of externally accessible pads. Each of the metal layers has a pair of pads. Using the pads coupled to the conductive trace, current is forced through each of the plug to metal interfaces and a voltage difference across each interface is measured in order to obtain the resistance of each interface. The total resistance of the inter-layer contact plug is similarly obtained and the resistance of the plug itself is obtained by subtracting the resistance of the two interfaces from the total resistance. The present invention enables the resistance of each of the interfaces and the plug to be separately determined to aid in troubleshooting a fabrication process used to form the metal layers and inter-layer contact structure of the semiconductor device.
申请公布号 US6013952(A) 申请公布日期 2000.01.11
申请号 US19980046113 申请日期 1998.03.20
申请人 LSI LOGIC CORPORATION 发明人 CHAN, KAM-KEE VICTER
分类号 H01L23/522;H01L23/544;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 主分类号 H01L23/522
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