| 摘要 |
A data segment synchronizing signal detecting circuit for reducing bit resolution of an HDTV without affecting its function. The apparatus includes a hard limiter added between a four-symbol correlator and an adder, to obtain a 2-bit output of three-level values for a four-bit input. The circuit may also include a first symbol delay for delaying an output of a symbol correlator by a factor N corresponding to a number of symbols of one segment, a first adder for adding the value delayed by the first symbol delay and the output of the symbol correlator, and accumulating the added result, a first maximum value location detector for detecting a first location of a first maximum value of the added result accumulated in the first adder, a second symbol delay for delaying the output of the symbol correlator by (one segment symbol)/N, according to the first maximum value detected by the first maximum value location detector, a second adder for adding the value delayed by the second symbol delay and the output of the symbol correlator, and accumulating the added result, a second maximum value location detector for detecting a second location of a second maximum value of the added result accumulated in the second adder, and a synchronizing signal generator for generating a segment synchronizing signal, according to an output of the second maximum value location detector.
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