| 摘要 |
A method and system for automatically stalling a pipeline of a processor to insure input/output (I/O) data integrity, where the processor has a write buffer and allows read instructions to bypass write instructions. Within the processor, write instructions are stored in a write buffer and read instructions are allowed, in certain circumstances, to bypass these stored write instructions. The present invention utilizes the operating system (OS) of a computer system to collect, in the page frame number (PFN) information, an indication as to whether or not a particular memory range is located in I/O memory space. The I/O memory space is defined as memory space that is used to communicate information to and from a peripheral device. When a memory address is placed into a translation lookaside buffer (TLB) of the processor, it is stored with the above indication. If this memory address is associated with a write instruction that becomes stored in the write buffer, the indication is copied into the write buffer. Each time a read instruction is processed by the processor, a check is made to determine if the read instruction is within I/O memory space. If not, the read is allowed to bypass any write instructions in the write buffer. If so, a check is made if any write instructions of the write buffer also involve I/O memory space. If not, the read is allowed to bypass any write instructions in the write buffer. If so, the read instruction is not allowed to bypass, and a pipeline stall is invoked to clear the write buffer. Then, the read instruction can proceed.
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