| 摘要 |
PROBLEM TO BE SOLVED: To provide a cell structure of a low-power static RAM which reduces the standby current and can control the data holding voltage. SOLUTION: This static RAM is constituted of a cell load control section 20 provided with a NAND gate ND21 for NANDing a data holding mode signal with a chip selecting signal/CS, an inverter INV21 for reversing the output of the NAND gate ND21, a PMOS transistor PM21 in which the output of the inverter INV21 is applied to a gate, external voltage VCC is applied to a source to output cell voltage VCE from a drain, a NMOS transistor NM21 in which external voltage VCC is applied to a gate and a drain, and a resistor RCL which is connected to the source of the NMOS transistor NM21 to output cell voltage VCE, of a data holding voltage detecting section 10, and of a load resistor cell 30.
|
