SPLIT DIRECTORY-BASED CACHE COHERENCY TECHNIQUE FOR A MULTI-PROCESSOR COMPUTER SYSTEM

摘要

A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor (16) cache in a multi-processor computer system (60) contains the same line of memory (50) which thereby reduces the searches required to perform the coherency operations and the overall size of the memory (50) needed to support the coherency system. The technique includes the attachmen t of a coherency tag (106) to a line of memory (104) so that its status can be tracked without having to read each processor (16) cache (102) to see if the line of memory (104) is contained within the cache (102). In this manner, on ly relatively short cache coherency commands need be transmitted across the communication network (68) (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed do wn by cache coherency data transmissions while removing the bandwidth limitatio ns inherent in other cache coherency techniques. The technique disclosed may be further expanded to incorporate the bus lock capability of bus-based systems compatible with the requirements for multi-processor synchronization.