| 摘要 |
<p>A method is provided for isotropically etching pairs of sidewall spacers (66a, 66b, 78a, 78b) to reduce the lateral thickness of each sidewall spacer (66a, 66b, 78a, 78b). In an embodiment, first and second pairs of sidewall spacers (66a, 66b) are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors (58a, 58b). The first and second gate conductors (58a, 58b) are spaced laterally apart upon isolated first and second active areas (46, 48) of a semiconductor substrate (50), respectively. Advantageously, a single set of sidewall spacer pairs (66a, 66b) are used as masking structures during the formation of source and drain regions (62, 74) of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain ('S/D') implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers (66a, 66b) prior to reducing the lateral thicknesses of the sidewall spacers (66a, 66b). However, the p- LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers (78a, 78b) after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers (66a, 66b, 78a, 78b) need not be formed laterally adjacent the sidewall surfaces of the gate conductors (58a, 58b) to vary the spacing between the implant regions (62, 74) and the gate conductors (58a, 58b) of the ensuing integrated circuit.</p> |
