| 摘要 |
An asymmetric arbiter provides a fast signal path and a slow signal path. Signals may travel over the fast signal path in substantially less time than it takes for the signals to travel over the slow signal path. The fast signal path may be configured so as to impart only a minimal amount of delay. Signals that are to be frequently arbitrated by the arbiter may be applied to the fast signal path so as to minimize the delay introduced by the arbiter. The arbiter may include circuitry for detecting metastable conditions.
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