| 摘要 |
<p>In a virtual ground type array comprising a number of electrically data-programmable, erasable memory cells, arranged matrix-wise in rows and columns; a multiple number of row lines, each connecting the control gates of memory cells located in one row; and a multiple number of column lines, each commonly connecting the drain and source of memory cells constituting columns, the memory cells are programmed starting sequentially in the order of degree of the difference in charge amount in the floating gate from the erased state (data '00'), <IMAGE></p> |
