| 摘要 |
<p>Apparatus (10) produces an output clock signal (CLKOUT) that is selectively synchronized to one of two generally free-running input clock signals (CLKA, CLKB) that may be of the same or different frequency and phase. The apparatus comprises first and second circuits (12, 14) which produce appropriately synchronized handshake signals to ensure that switching occurs between the two input clock signals in a manner whereby the output clock signal does not have any clock pulses that are shrunk or narrowed. <IMAGE></p> |
