| 摘要 |
A method for queuing hardware control blocks for a system including a host microprocessor and a plurality of devices that each includes an onboard sequencer is based on a single host endless new hardware control block queue in a host memory that is managed such that the host endless new hardware control block queue never goes empty. Each device, that is coupled to the host microprocessor by an I/O bus, also has a device endless new hardware control block queue in a common hardware control block array. These device endless new hardware control block queues are managed such that the queues never are empty. A single device on the bus fetches hardware control blocks from the host endless hardware control block queue and loads the hardware control blocks in the common hardware control block array. The other devices on the I/O bus do not participate in the transfer of hardware control blocks to the common hardware control block array.
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