发明名称 |
Method and apparatus for indicating overflow status of bit-variable data employing pipelining adder |
摘要 |
An apparatus and a method for indicating the computational adder overflow status of bit-variable data employing a pipelining adder. An adder is provided with a first input port and a second input port, for adding a multiple-bit data input from the second input port. A plurality of shift registers receive and store in parallel a plurality of multiple-bit data output from the adder, and sequentially output the plurality of multiple-bit data to the second input port of the adder in response to a clock signal. A comparing circuit simultaneously receives and compares a multiple-bit data output from the adder and a multiple-bit data output from a plurality of shift registers. An overflow arbitrating unit arbitrates the overflow status of each multiple-bit data in accordance with a comparing result from the comparing circuit as well as a selective signal.
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申请公布号 |
US6012077(A) |
申请公布日期 |
2000.01.04 |
申请号 |
US19950511540 |
申请日期 |
1995.08.04 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
TAI, CHIAO-YEN |
分类号 |
G06F7/50;G06F7/509;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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