ESD protection apparatus having floating ESD bus and semiconductor structure

摘要

An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus VDD. The ESD bus is coupled to the negative power supply bus VSS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to VSS. The threshold voltage is selected such that, in normal operation, voltages higher than VDD may be applied to the input pad without input leakage current.