| 摘要 |
PROBLEM TO BE SOLVED: To reduce the current consumption at the time of a power down mode by generating periodic signals of a constant pulse width changing periodically in synchronization with external clock signals and generating internal clock signals corresponding to the output of an initial stage circuit. SOLUTION: At a power down mode, a third initial stage circuit, the other initial stage circuits are inactivated, and a synchronous operation of an internal circuit executing a control command is stopped. Each node of a CMOS circuit holds data, and the current consumption because of charging, discharging is gone. The third initial stage circuit, the other initial stage circuits are inactivated by a control signalϕ7 and the current consumption is cut to be zero. Only a first initial stage circuit, a first one-shot signal generation circuit operate at this time synchronously with an external clock signal CLK, and moreover, the size of each transistor constituting these circuits can be designed to the minimum to meet the load capacity of a periodic signalϕ3, so that the current consumption by charging, discharging of each node in the circuits is greatly reduced.
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