发明名称 Test structure for measurement of multilayered interconnect capacitance for VLSI technology
摘要 Structure for testing multilayer integrated circuits, where each layer has its own conducting tracks. The test structure comprises an ammeter (7) connected between a power input (8) and an earth (6) and at least two circuit branches. Circuit breakers (9,11) are arranged so that the capacitance between two circuit tracks (1,2) can be determined. The first branch comprises a first breaker (9) between the ammeter and a first track (1), and the second branch has a similar arrangement of breaker between ammeter and second track (2).
申请公布号 FR2780162(A1) 申请公布日期 1999.12.24
申请号 FR19980007788 申请日期 1998.06.19
申请人 STMICROELECTRONICS SA 发明人 FROMENT BENOIT
分类号 G01R27/26;G01R31/28;(IPC1-7):G01R31/28;G01R27/16 主分类号 G01R27/26
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