| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a fast data transfer system which can conduct fast transfer of the data without increasing the number of pieces of wiring of a data bus. SOLUTION: The memory modules 2 and a controller 3 are arrayed and two pieces of clock wiring 4A and 4B are set along the array of modules 2 and controller 3 in a reciprocating way. A 1st basic clock TCLK and a 2nd basic clock TCLK2 having a double cycle of that of the TCLK are supplied to the modules 2 and controller 3 via the going wiring 4A and 4B. Meanwhile the 1st and 2nd return basic clocks RCLK and RCLK2 pass through the turning point and are supplied to the modules 2 and controller 3. The clocks TCLK, TCLK2, RCLK and RCLK2 are fetched by the modules 2 and controller 3. Then the input/output operations of data are controlled synchronously with those basic clocks.</p> |
