| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock hardware scale distributing device which is inexpensive and small and is capable of shortening the processing halt time at the time of clock switching by providing a synchronized transmission means with n-fold phase for outputting the result obtained by multiplying the frequency of a selected clock by (n), and supplying the result obtained by further multiplying by (n) to a processing unit and a system control means or the like for operating the active/standby switching of an information processor. SOLUTION: At a processor #0, for example, the clock frequency is increased by a PLL 8 after an active/standby clock selector circuit, and plural PLL 10-12, after the outputted clock further increase the clock frequency and supplied to the processing unit. A system control circuit 20 sends a control signal to a system control circuit 120 and performs the selection of active/standby clock of the processor #0, reset, start/stop and the active/standby switching operation of the processor corresponding to information from the system control circuit 120. Besides, all the phase-matched signals of PLL 10-12 on the final step are detected and reported to the system control circuit 120. |
