| 摘要 |
PROBLEM TO BE SOLVED: To prevent current consumption owing to a sub-threshold leakage with a logical circuit even when plural latch circuits exist in a semiconductor integrated logical circuit. SOLUTION: A state is normally fixed to be the one where a low potential clock signalϕ(ϕ='0') and a high potential inversion clock signal *ϕ(*ϕ='1') are previously impressed. When a mode is shifted to the sleep one (SL='1' and SLB='0') in a state where the output of an inverter circuit INV2A is '1' and the output of the inverter circuit INV2B is '0', a direct current caused by the sub-threshold leakage is leaked. But the leakage current is prevented by a switching element (transmission gate) TM3A without the sub-threshold leakage because of the configuration of a non-conductive state high threshold value transistor so that it does not flow from the latch circuit 10A to the logical circuit.
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