FUNCTIONAL VERIFICATION OF INTEGRATED CIRCUIT DESIGNS

摘要

A functional verification system suited for verifying the function of cycle based integrated circuit (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential element (110). Truth tables corresponding to the divided blocks are computed (120) and stored in a memory (130). The output values of the IC design are determined by evaluating the blocks (140). The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage (140). Accordingly the output values are computed quickly. The storage is implemented using random access memories and a cross-connect (XCON) is designed to ensure the dependencies of inputs and outputs are preserved during the evaluations (150).