High precision summing circuit for digital signal processing system

摘要

The summer circuit has a summing stage (101) that receives an input datum and a preceding sum and performs a bit shift on the input and sum data depending on a first or second bit shift control signal and adds the bit-shifted data to produce an instantaneous sum datum and output a part of the resulting datum as a shift-bit-computation datum. A shift bit search stage (103) outputs the first and second control signals to the summation stage for the addition of the next input datum and the current resulting datum based on the shift bit computation datum. An Independent claim is also included for a method of summing a number of input data items.