发明名称 Analog signal processing circuit with integrated gain and timing error signal processing
摘要 A Class IV Partial Response Maximum Likelihood data channel for analog signal processing of a disk drive signal in tracking mode includes a signal error generating circuit for "folding" the analog disk drive signal around the three PR-IV target values of +1, -1 and 0. Using the smaller error signal rather than the larger analog disk drive signal by which the disk drive signal deviates from the target values results in significant power saving with no reduction in electronic signal to noise ratio. An integrated error generating circuit generates both a gain error signal and a timing error signal from the folded error signal for feedback control of the data channel variable gain amplifier and variable clock oscillator. Shared processing of the timing and gain error signals results in power savings and simpler circuitry.
申请公布号 US6005729(A) 申请公布日期 1999.12.21
申请号 US19970891378 申请日期 1997.07.11
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 POSS, JOE MARTIN
分类号 G11B5/012;G11B5/09;G11B20/10;G11B20/14;H04L7/02;(IPC1-7):G11B5/09 主分类号 G11B5/012
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