| 摘要 |
A memory device provides for multi-way set associative burst SRAM (static random access memory) cache memory in a single device or package. In one embodiment input address bit A2 is used to generate a bank select signal rather than as a direct input to the SRAM's memory array element. This, in combination with additional output registers and output buffers creates a two-way set associative cache memory in a single memory device. In an alternative embodiment, input address bits A2 and A3 are used to generate bank select signals rather than as direct input to the SRAM's memory array element. This, in combination with additional output registers, output buffers, and an output bank decoder creates a four-way set associative cache memory in a single memory device. Additionally, a mode circuit is provided that controls whether the memory device operates as a multi-way set associative memory or as a conventional direct-mapped memory device. The mode circuit provides backwards compatibility with existing burst SRAM devices.
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