发明名称 |
Digital-type delay locked loop with expanded input locking range |
摘要 |
A low-jitter delay locked loop having an expanded phase locking range without the necessity of setting the initial delay is provided. The loop is to be supplied by a system clock and includes a pulse generator receiving the system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal, a delay device receiving the system clock for providing a delayed clock in response to a control signal, a frequency-reducing device for frequency-reducing the system clock into a first clock in response to the first pulse signal and frequency-reducing the delayed clock into a second clock in response to the second pulse signal, and a comparator for comparing the first and second clocks to generate the control signal.
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申请公布号 |
US6005426(A) |
申请公布日期 |
1999.12.21 |
申请号 |
US19980073746 |
申请日期 |
1998.05.06 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
LIN, JYHFONG;LIN, HSIN-CHIEH |
分类号 |
H03L7/081;H03L7/10;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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