发明名称 HIGH SPEED AND LOW DRIFT CHARGE PUMP CIRCUIT
摘要 A device for converting binary logic pulses into an output current and the output current being switchable between a positive and negative polarity. The device provides a charge pump circuit which is suitable for the phase-detector stage in a phase-locked loop (PLL) circuit. The charge pump circuit comprises an input stage for the "UP" binary logic pulses and a second stage for the "DOWN" binary logic pulses. The input stages comprise emitted-coupled transistor pairs. The circuit includes current sources and current sinks for generating the output current in the input stages in response to the binary logic pulses. The circuit features a pair of commutating diodes between the outputs of the input stages. The commutating diodes control the output current and the leakage current in the idle state. The circuit also includes a clamping circuit to limit the voltage swing across the commutating diodes. The charge pump circuit according to the present invention exhibits a fast response time, a symmetrical response to the binary logic pulses, and virtually zero leakage current in the idle state. The charge pump circuit utilizes non-complimentary bipolar processes and is suitable for a monolithic integrated circuit implementation.
申请公布号 CA2113762(C) 申请公布日期 1999.12.21
申请号 CA19942113762 申请日期 1994.01.19
申请人 发明人 WEBSTER, STEPHEN
分类号 H03L7/093;G05F3/22;H02M3/07;H03L7/089;(IPC1-7):H03L7/085 主分类号 H03L7/093
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