Phase adjustment circuit including a ring oscillator in a phase locked loop

摘要

A phase adjustment circuit includes a ring oscillator which is phase locked to an external pixel clock by a phase locked loop. The ring oscillator is formed of n number of stages of variable delay circuits providing n+1 outputs of substantially equal phase differences. A control signal generation circuit is responsive to a phase control signal to generate n+1 weighting coefficients for weighting the n+1 outputs from the ring oscillator in a weighting circuit which produces a phase adjusted output signal.