| 摘要 |
A product sum operation apparatus in which an increase in the circuit scale of the product sum operation apparatus can be suppressed and the operation speed can be increased even when the number of bits to be operated is increased. A partial product generating circuit has a partial product operation circuit of 12 bitsx24 bits structure. A multiplier is divided into a lower digit multiplier of lower 12 bits and an upper digit multiplier of upper 12 bits. The partial product generating circuit receives sequential outputs from each of the lower digit multiplier and upper digit multiplier to generate corresponding lower digit partial products and upper digit partial products. An adder circuit adds the lower digit partial products, and the results of addition are temporarily held in a register of 48 bits structure. The adder circuit adds the lower digit addition results delivered out of the register, the results of upper digit addition of the upper digit partial products and an augend/minuend to generate a product sum operation result.
|
