Test mode features for synchronous pipelined memories
摘要
An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.
申请公布号
US6006347(A)
申请公布日期
1999.12.21
申请号
US19970932637
申请日期
1997.09.17
申请人
CYPRESS SEMICONDUCTOR CORPORATION
发明人
CHURCHILL, JONATHAN F.;RAFTERY, NEIL P.;HENDRY, COLIN J.;SHANMUGAM, JEYAKUMAR;FINN, MARK A.;SURRETTE, THOMAS M.;PHELAN, CATHAL G.;PANCHOLY, ASHISH