| 摘要 |
A clock delay circuit which creates control signals relative to a clock signal which vary in relation to inherent variables arising from manufacturing process, temperature and voltage influences on a memory array. The clock delay circuit preferably comprises a pair of spare word lines and a pair of spare bit lines of the memory, each of which extends across the memory array. Signals conducted along the spare word and bit line create a signal which is supplied to a counter and decoder to supply a plurality of control signals having a timing relationship established relative to the clock. The spare word line and spare bit line comprise electrical characteristics affecting signal propagation time similar to a signal propagation time along one of an actual word line or actual bit line, respectively.
|
