Serial multi port memory component comprising RAM memory bank assemblies for use in computer

摘要

Each memory bank (RAMi) is associated with a shift register (RDMi) allowing the writing or reading of a block of data from the memory bank every memory cycle. All the I/O interfaces of the registers are connected to a series of external data I/O ports (Bd1...Bdn), via a bidirectional logic crossbar (CB), so that temporary pathways are set up the assembly elements. The arrangement allows simultaneous execution of multiple read write operations on blocks of data.