| 摘要 |
<p>A SIGMA - DELTA analog-to-digital converter (ADC) 210 includes a multibit SIGMA - DELTA modulator 216 and a feedback loop 240, 241 including a digital-to-analog converter (DAC) 241. A nonlinear filter corrector 250 coupled to the multibit output port 216o of the modulator 216 includes a transversal filter 252, weighting multipliers 256 coupled to the taps 254 of the transversal filter 252, and a summing arrangement 258, 260 coupled to the multipliers, for creating a correction signal based on an estimate of the dynamic errors of the SIGMA - DELTA ADC. A calibration arrangement 280 applies an alternating calibration signal to the input port 212 of the SIGMA - DELTA ADC 210, and determines, from the output signal of the modulator 216 and from the known delays L of the delay elements of the transversal filter 252, the values of the weights required to correct dynamic errors of the DAC. In one version, the weighting multipliers are look-up tables. <IMAGE></p> |
