| 摘要 |
An interpolation circuit for a digital filter which is small in circuit scale, operates at a high speed and is low in power consumption. The digital interpolation filter circuit includes front-end circuit 1 which outputs added value SIGMA i of input data and the last data, and filter unit 2. Filter unit 2 includes delay circuit unit 3 which delays added value SIGMA i of one clock and two clocks intervals, and outputs the delayed values, bit shift circuit unit 4 which inverts the signs of the added value and data obtained by delaying the added value 2 clocks interval and outputs resulting values and which shifts the data delayed one clock interval from the added value, 3 bits and one bit making multiplication of the delayed added value by 8 and 2, respectively, and outputs resulting values, adder 5 for adding the outputs of bit shift circuit unit 4 for each data having the same delay amount, and bit shift circuit 6 for shifting a result of the addition by 4 bits to divide the addition result by 16.
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