| 摘要 |
An input buffer circuit of a semiconductor memory device in which data is accessed by driving a decoder based on first and second internal address signals, the input buffer circuit including a first circuit for summing an input address and a chip selection signal to generate a first address signal, first and second inverters for inverting the first address signal and generating the first internal address signal and a second address signal, a detector circuit receiving the first internal address signal and the second address signal and detecting a HIGH of the first internal address signal and a LOW of the second address signal, and a second circuit for summing an output of the detection means and the second address signal and generating the second internal address signal.
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