发明名称 |
Performance optimizing compiler for building a compiled SRAM |
摘要 |
A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
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申请公布号 |
US6002633(A) |
申请公布日期 |
1999.12.14 |
申请号 |
US19990225075 |
申请日期 |
1999.01.04 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
OPPOLD, JEFFERY H.;OUELLETTE, MICHAEL R.;SULLIVAN, MICHAEL J. |
分类号 |
G11C8/12;(IPC1-7):G11C8/00;G11C11/00 |
主分类号 |
G11C8/12 |
代理机构 |
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主权项 |
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