| 摘要 |
A processor and coprocessor architecture wherein the coprocessor is put into operation at a cycle immediately following the decoding of an instruction code by the recognition, during this decoding, of the fact that this instruction is an instruction that has to be carried out by the coprocessor. The complementary decoding of the instructions makes it possible to lose no time in the configuration of the coprocessor. This type of architecture is particularly useful for digital processors entrusted with carrying out certain specific operations, notably audio processing operations.
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